The invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having writable memory cells, a pair of bit lines which connect the memory cells to a differential sense amplifier that is used to transfer data which are to be read during a read access operation from the memory cells to outside the memory, and that is used to transfer data which are to be written during a write access operation from outside the memory to the memory cells. The integrated memory further has a control unit for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation.
Differential sense amplifiers are used, for example, in DRAMs and FRAMs (ferroelectric RAMs) for amplifying data read from memory cells and for writing data to the memory cells. U.S. Pat. No. 5,241,503 describes such a sense amplifier. It is connected to the memory cells by means of a bit line pair used to transfer a difference signal. Before a read access operation, the bit lines are precharged to particular potentials before one of the memory cells is conductively connected to one of the bit lines and influences the potential thereof. Next, the sense amplifier is activated, so that it amplifies the potential difference between the two bit lines, and the bit lines then have opposite logic levels. Since the memory cell content of a DRAM memory cell is lost when the memory cell is read (destructive reading), the signal amplified by the sense amplifier during read access is usually written back to the previously read memory cell. In this manner, the original memory state thereof is restored.
In a DRAM or FRAM, a write access operation differs only slightly from a read access operation. The main difference is that, for a read access operation, the sense amplifier forwards the amplified difference signal to outside the memory, whereas, for a write access operation, a difference signal corresponding to an item of data which is to be written is supplied from outside the memory to the sense amplifier, which sets appropriate potential states on the bit line pair connected to it. Both at the start of a read access operation and at the start of a write access operation, the bit lines are usually precharged in the same way, i.e. using the same steps. A write access operation and a read access operation therefore differ only in terms of whether, when the bit lines have been precharged, the sense amplifier transfers data supplied from outside the memory to the bit lines, or whether the sense amplifier amplifies the difference signal produced on the bit line pair when the memory cell is read and forwards it to the outside.
The execution just described for a write cycle and a read cycle in a DRAM or FRAM has the advantage that the control for precharging the bit lines and for conductively connecting the memory cells to one of the bit lines is effected in exactly the same way in both cases. Hence, a write access operation in the conventional memories with destructive reading takes just as long as a read access operation.
U.S. Pat. No. 5,487,043 discloses a memory in which bit lines are precharged to a precharge potential by means of a signal which carries out charge equalization at the same time using two transistors.
The object of the present invention is to provide an integrated memory with a differential read amplifier which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which allows fast write access to take place.
With the above and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
writable memory cells;
a differential sense amplifier configured to transfer data read during a read access operation from the memory cells to outside the memory, and to transfer data to be written during a write access operation from outside the memory to the memory cells;
a pair of bit lines connecting the memory cells to the differential sense amplifier;
a control unit connected to the bit lines for precharging the bit lines in a given number of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation; and
the control unit precharging the bit lines during a write access operation with fewer than the given number of steps before the sense amplifier transfers data to the bit line pair.
In other words, the integrated memory according to the invention has writable memory cells. It also has a pair of bit lines which connects the memory cells to a differential sense amplifier which is used to transfer data which are to be read during a read access operation from the memory cells to outside the memory, and which is used to transfer data which are to be written during a write access operation from outside the memory to the memory cells. In addition, it has a control unit for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.
Since the precharging of the bit lines which is carried out for a read access operation is dispensed with either completely or at least partly for a write access operation, a write access operation is advantageously obtained which requires less time for its execution than for executing a read access operation. The memory according to the invention can thus be written to faster than conventional memories.
The invention can be used generally for writable integrated memories containing differential amplifiers.
In accordance with an added feature of the invention, memory cell contents of the memory cells are destroyed, i.e., erased, during a read access operation; and the sense amplifier amplifies a difference signal established on the bit line pair when the memory cell has been conductively connected to the bit line during the read access operation, and then writes the difference signal back to the memory cell.
In this development, the memory cell contents of the memory cells are erased during a read access operation, that is to say that destructive reading is involved. During a read access operation, the sense amplifier amplifies the difference signal established on the bit line pair when the memory cell has been conductively connected to the bit line, and then writes it back to the memory cell.
Memories with destructive read access operations are DRAMs and FRAMs, for example. In these memories, the memory access operation is terminated by writing data to the memory cells, both in the case of reading and in the case of writing. According to the invention, for a write access operation, no more than some of the steps required for precharging the bit lines during a read access operation are executed for a write access operation. This means that a write access operation differs from the read access operation in terms of the precharging steps preceding the writing which takes place for both types of access.
In accordance with an additional feature of the invention, the control unit, in order to precharge the bit lines for the read access operation, precharges both bit lines of the bit line pair to a common potential, and the common potential is dispensed with for the write access operation.
In accordance with another feature of the invention, the control unit performs two operations for the read access operation for precharging the bit lines, including reading out reference memory cells onto the bit lines and then performing a charge equalization between the bit lines, but both operations are dispensed with for a write access operation.
In accordance with a further feature of the invention, the control unit, in order to precharge the bit lines for the read access operation, discharges the bit line connected to the memory cell which is to be read, the discharge being effected subsequently to the charge equalization between the bit lines and being dispensed with for the write access operation.
In accordance with a concomitant feature of the invention, during the read access operation, the respective the memory cell is read by conductively connecting the memory cell to one of the bit lines before the sense amplifier is activated; and during a write access operation, the sense amplifier is activated first, so that data to be written are already present on the bit line pair before the respective the memory cell is conductively connected to one of the bit lines.
In accordance with the further development of the invention, during a read access operation, the respective memory cell is read by conductively connecting it to one of the bit lines before the sense amplifier is activated. In addition, during a write access operation, the sense amplifier is activated first, so that data which are to be written are already present on the bit line pair before the respective memory cell is conductively connected to one of the bit lines.
Hence, whereas read access takes place as in conventional DRAMs or FRAMs, for a write access operation, the sense amplifier is activated first before the memory cell is conductively connected to one of the bit lines. This has the advantage that, following activation of the sense amplifier and the associated possible charge reversal on the bit line, there is no need to wait as long until the respective memory cell is actually conductively connected to the appropriate bit line. To write an item of data to one of the memory cells after the sense amplifier has been activated, it is then sufficient for the memory cell to be briefly conductively connected to the appropriate bit line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a differential sense amplifier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.